ISCA 2022

A tutorial on LoopPoint and ELFies has been accepted to the International Symposium on Computer Architecture (ISCA) 2022, which will be held in New York City on 18-22 June 2022. The authors are looking forward to sharing this work and having an in-person discussion during the tutorial session.

The tutorial is based on our recently published research to demonstrate how to effectively reduce the simulation time of large multi-threaded applications to a practically short period of time. This is a key issue for future large-system exploration, both in the industry as well as academia. In this tutorial, we will demonstrate a collection of tools and techniques that are intended to help computer architecture researchers simulate complex applications on future hardware (with a focus on our most recent publication, LoopPoint, from HPCA 2022). The tutorial targets researchers interested in simulation methodologies, workload sampling, application analysis, and computer architecture in general. The tutorial covers several interesting and novel methodologies developed in industry as well as academia.

You can find the source code at GitHub: LoopPoint and ELFies

Slides

The tutorial slides are posted here.

Agenda

The tutorial is scheduled for Sunday, June 19 2022 after lunch in Columbus Circle (lower level) at Sheraton New York Times Square Hotel.

13.20 to 13.30 Alen starts the tutorial with an overview
13.30 to 14.30 Harish talks about Pin, PinPlay, SDE, ELFies
14.30 to 15.00 Break
15.00 to 15.45 Wim talks about performance analysis, simulation using Sniper multicore simulator
15.45 to 16.45 Alen talks about single-threaded and multi-threaded sampling, LoopPoint
16.45 to 17.15 Alen conducts a demo to use LoopPoint/ELFies

Speakers

LoopPoint and ELFies was done as a collaboration project between the National University of Singapore (NUS) and Intel Corporation. There are several people involved in the project both from NUS and Intel. The primary contributors of the project are listed below.

Alen Sabu

Alen is a PhD candidate in computer science at the National University of Singapore. His research interests lie broadly in the areas of computer architecture, performance analysis, and distributed systems. His current research focus is on speeding up the architectural simulation of multi-threaded applications.


Harish Patil

Harish Patil is a Principal Engineer in a Technology Path-finding and Innovation group at Intel Corporation. His areas of interest include static/dynamic program analysis (using “Pin/SDE” and “LLVM”), simulation point selection(“PinPoints”), record/replay (“PinPlay”), and debugging (“DrDebug”). Recipient of “ACM Programming Languages Software Award:2020” for co-developing the Pin program instrumentation framework. Co-author of two papers with “Test-of-Time” awards based on Pin (PLDI 2005-2015) and PinPlay (CGO 2010-2020). He has a Ph.D. from the University of Wisconsin, Madison, a B.Tech. and an M.Tech. from Indian Institute of Technology, Bombay, and an MBA from Babson College.


Wim Heirman

Wim Heirman is a research scientist at Intel Corporation. His research interests include fast and accurate simulation, and computer architecture design and exploration. He co-authored the Sniper Multi-Core Simulator, has written 100+ papers in scientific conferences and journals, and has 10 granted US patents. He received a M.Sc (2003) and Ph.D (2008) in computer engineering from Ghent University, Belgium.


Trevor E. Carlson

Trevor E. Carlson is an assistant professor at the National University of Singapore (NUS). He received his B.S. and M.S. degrees from Carnegie Mellon University in 2002 and 2003, his Ph.D. from Ghent University in 2014, and has worked for 3 years as a postdoctoral researcher at Uppsala University until 2017. He has over 13 years of computer architecture experience covering both industry and academia. His work on microarchitecture, simulation, sampling and modeling has seen three Best Paper Awards and three nominations for Best Paper. He has been developing techniques for high-efficiency processors that improve energy efficiency and performance by taking into account Memory Level Parallelism (MLP) together with unique architectural designs and software techniques. He co-authored the Sniper Multi-Core Simulator which has been used by hundreds of researchers to evaluate the performance and power efficiency of next-generation systems. His research interests include highly-efficient microarchitectures, hardware/software co-design, performance modeling, and fast and scalable simulation methodologies.

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